A. Field of the Invention
The present invention relates to a superjunction semiconductor device with a high breakdown voltage and high current capacity applicable to a MOSFET (metal oxide semiconductor field effect transistor), IGBT (insulated gate bipolar transistor), bipolar transistor, or the like, and to a manufacturing method of the device. In the following description, the superjunction semiconductor device refers to a semiconductor device wherein a drift layer, in which a p-type region and n-type region of a column-shape or layer-shape deposited in a vertical direction to a main surface of a semiconductor substrate form alternately adjacent parallel pn layers in a direction along the main surface, has a function to flow a current in an “on” state and to hold a breakdown voltage in an “off” state.
B. Description of the Related Art
In general, semiconductor devices are classified into a lateral semiconductor device that has an electrode on only one surface of a semiconductor substrate where a current flows along a main surface, and a vertical semiconductor device that has electrodes on both surfaces of a semiconductor substrate where a current flows between electrodes on main surfaces. In the vertical semiconductor device, the direction in which a drift current flows in the “on” state of the device is the same as the direction in which a depletion layer extends due to a reverse bias voltage in the “off” state of the device. In the case of a conventional planar n-channel vertical MOSFET, a high resistivity n-drift layer works for flowing a drift current in a vertical direction in the “on” state of the MOSFET, and is depleted in the “off” state to hold a breakdown voltage. Shortening the current path of the high resistivity n-drift layer, that is, making the high resistivity n-drift layer thinner, leads to an effect of lowering the on-resistance of the MOSFET due to the decreased resistance in the n-drift layer. However, as the width of a depletion layer spreading from a pn junction between a p-type base region and the n-drift layer decreases, the electric field strength quickly reaches the critical electric field of silicon and the breakdown voltage decreases. On the other hand, an n-channel vertical MOSFET with a high breakdown voltage has a thick n-drift layer and the thick n-drift layer leads to a high on-resistance, and the conduction loss of the MOSFET increases. This relationship between the on-resistance and the breakdown voltage is called a trade-off relationship. It is known that this trade-off relationship exists in semiconductor devices such as an IGBT, bipolar transistor, or diode as well.
Meanwhile, in order to realize a high breakdown voltage in a vertical semiconductor device, the device needs a peripheral region in a ring shape surrounding an active region through which a current flows. Without this peripheral region, it is difficult to realize the high breakdown voltage, because an electric field strength becomes high in the outer region of the drift layer, which leads to the breakdown voltage decrease. Also, even though the breakdown voltage is initially maintained, the device with low robustness against surface charge is difficult to guarantee the reliability of the breakdown voltage. The surface charge on the peripheral region affects the extension of the depletion layer, which results in the breakdown voltage decrease with the passage of time. Hereafter, a semiconductor device with high robustness against surface charge refers to the semiconductor device in which the initial breakdown voltage is maintained even with the passage of time, that is, the semiconductor device with high reliability. In order to solve the problem of the breakdown voltage decrease in reliability, a semiconductor device with a guard ring connected to a forward and reverse direction Poly-Si field plate in peripheral region is generally known. Regarding the semiconductor device having this type of peripheral region, the influence on the extension of the depletion layer near the surface is weakened, even when a positive charge or a negative charge exists on the surface in the peripheral region. As a result, the breakdown voltage degradation is suppressed and the robustness against surface charge is improved.
Furthermore, it is desirable that a peripheral region is as narrow as possible in light of the efficiency of semiconductor material use because the peripheral region is an inactive region. Relating to this point, there is disclosed a semiconductor device in which the width of a peripheral region in a straight section is decreased and the area of the active region is increased commensurately by adopting the configuration with a p-type guard ring, a first field plate and a second field plate at the same electric potential in a corner section of the peripheral region (JP-A-2008-193043).
Furthermore, a semiconductor device has been disclosed in which it is possible to narrow the intervals between the plurality of field plates by adopting the configuration with a plurality of guard rings formed in a peripheral region, a polysilicon field plate placed on an insulating film in the inner and outer circumferential side of each guard ring, and an aluminum electrode connecting the guard rings and field plates (JP-A-2009-117715 (abstract and FIG. 1)).
However, with the MOSFET described in JP-A-2009-117715 (abstract and FIG. 1), although high relaxation of electric field and high robustness against induced surface charges with a narrow width in a peripheral region, it is necessary to form the p-type guard rings before forming the polysilicon field plates. In this case, in the process of forming a p-type base region and the p-type guard rings after forming a polysilicon gate and the polysilicon field plate, photolithography and ion implantation steps for forming the p-type guard rings need to be added. As these additional steps not only increase the manufacturing cost but also, as a misalignment of the p-type guard rings and polysilicon field plates is liable to occur, become a cause of a fluctuation or deterioration of the electric field relaxation capability and the low robustness against induced surface charge, it is desirable, as far as possible, that there is no additional step of this kind.
Also, with the MOSFET described in JP-A-2003-115589, when an n-type surface region with a low impurity concentration is formed on parallel pn layers with a high impurity concentration, autodoping from a substrate to the n-type surface region is unavoidable, meaning that it is difficult to control the impurity concentration of the n-type surface region. As a substrate doped with As is particularly liable to outdiffuse, there is a large effect on the impurity concentration of the n-type surface region, which is one factor in fluctuation of the impurity concentration of the n-type surface region. When the impurity concentration of the n-type surface region is not controlled, not only the maintenance of reliability on breakdown voltage, but also the maintenance of initial breakdown voltage becomes difficult.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.